I. Field
The present invention relates generally to data communication, and more specifically to techniques for reducing leakage current in complementary metal oxide semiconductor (CMOS) circuits.
II. Background
Integrated circuit (IC) fabrication technology continually improves and, as a result, the size of transistors continues to shrink. This enables more transistors and more complicated circuits to be fabricated on an IC die or, alternatively, a smaller die to be used for a given circuit. Smaller transistor size also supports faster operating speed and provides other benefits.
For CMOS technology, which is widely used for digital circuits and some analog circuits, a major issue with shrinking transistor size is standby power. A smaller transistor geometry results in higher electric field, which stresses a transistor and causes oxide breakdown. To decrease the electric field, a lower power supply voltage is often used for smaller geometry transistors. Unfortunately, the lower power supply voltage also increases the delay of the transistors, which is undesirable for high-speed circuits. To reduce the delay and improve operating speed, the threshold voltage (Vt) of the transistors is reduced. The threshold voltage determines the voltage at which the transistors turn on. However, the lower threshold voltage and smaller transistor geometry result in higher leakage current, which is the current passing through a transistor when it is turned off.
Leakage current is more problematic as CMOS technology scales smaller. This is because leakage current increases at a high rate with respect to the decrease in transistor size. Moreover, leakage current is a major issue for certain applications such as portable devices (e.g., cellular phone and portable computer). Leakage current consumes power and reduces standby time for portable devices that use battery power.
Reducing leakage current without sacrificing too much performance is one of the major challenges in CMOS designs, especially as IC technology scales down to 90 nm (nanometer) and smaller. One common method of combating high leakage current in large CMOS circuit designs is to cut off power to a CMOS circuit when it is turned off. Power may be cut off with a head switch, a foot switch, or both. A head switch is a switch placed between a power supply and the CMOS circuit. A foot switch is a switch placed between the CMOS circuit and circuit ground.
A dual-Vt CMOS technology allows for fabrication of both low threshold voltage (low-Vt) and high threshold voltage (high-Vt) field effect transistor (FET) devices on the same IC die. Since speed is not critical for head and foot switches, these switches may be implemented with high-Vt FET devices to reduce leakage current. The CMOS circuit is implemented with low-Vt FET devices for high-speed operation. During normal operation, the switches are turned on and the CMOS circuit operates with the speed advantage of the low-Vt FET devices. In a standby mode, which is also referred to as a sleep mode, the switches are turned off and the CMOS circuit is disabled. Since the leakage current of a high-Vt FET device may be as much as 10 to 100 times less than the leakage current of a low-Vt FET device, leakage current of the CMOS circuit is reduced by the use of high-Vt FET devices for the switches.
The method described above for reducing leakage current (i.e., with high-Vt FET devices for the switches and low-Vt FET devices for the CMOS circuit) is adequate for some CMOS circuits. However, disconnecting the power supply with a head switch and/or circuit ground with a foot switch may be detrimental for certain CMOS circuits. One such CMOS circuit is a static random access memory (SRAM) with memory cells implemented with FET devices. For the SRAM, disconnecting the power supply and/or circuit ground causes the FET devices to float, which may cause the memory cells to lose their internal states. Consequently, data may be lost when the SRAM is placed in the standby mode.
There is therefore a need in the art for techniques to reduce leakage current for CMOS circuits such as SRAM.